Research

Current Projects

• Towards Automated Microelectronic Package Design
• Inhomogeneous Inclusion Design in Electromagnetic and Photonic Nanosystems
• Incorporating Statistical Variability into Circuit-Electromagnetic Modeling of RF and Analog Systems
• Enabling RF and Analog Synthesis Capability in Circuit-Electromagnetic Simulators
• Hybrid Numerical-Analytic Techniques for Power Integrity and Signal Integrity Modeling of Microelectronic Systems
• Cross Layer Circuit-Electromagnetic-Channel-Network Simulators for RFID System Design
• Design Tools and Insights for Low-Intensity Wireless Power Systems
• Discrete Green’s Function Methods for Accelerated and Novel Algebraic Algorithms on Graphs

Towards Automated Microelectronic Package Design

Student: Arun Sathanur

Funding: Intel SRS Grant, Intel Fellowship

Microelectronic package design has moved into the mainstream of microelectronic design owing to strong coupling effects, greater functionality, and increased demands by high-speed interfaces and low-power paradigms. While package simulation using electromagnetic simulation is in itself a challenging goal, we focus on a significantly more challenging problem and level: automating package design. We show how to exploit recent advances in rapid electromagnetic simulation to build an automated design and optimization layer around multiple variables. We study multi-dimensional response surface generation, multiscale optimization, as steps towards the eventual goal of package synthesis. Even with the use of fast solvers, the large number of parametric variables creates a high dimensionality design space and makes the overall optimization procedure, with the electromagnetic solver in the loop, extremely expensive.

Key Papers and Presentations

A. V. Sathanur, V. Jandhyala, K. Aygun, H. Braunisch, and Z. Zhang, "Optimization of vertical interconnect of a microprocessor package using a fast full-wave electromagnetic analysis tool," in Abstracts Progress in Electromagnetics Research Symp. (PIERS), Cambridge, MA, July 2-6,2008, p. 388.

A. V. Sathanur, V. Jandhyala, K. Aygun, H. Braunisch, and Z. Zhang, " Return Loss Optimization of the Microprocessor Package Vertical Interconnect," Electrical Components Technology Conference, San Diego, May 26-29,2009. [pdf]